Skip to content
Vinony

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design

by Stuart Sutherland

Cover of RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
Popularity 7

xxxi, 453 pages : 23 cm

Verilog (Computer hardware description language)Electronic digital computers -- Design and constructionComputer simulation