Category
page 2Computer memory

data redundancy
presence of data additional to the actual data that may permit correction of errors in stored or transmitted data
sequential access memory
memory timings
timing information of a memory module
memory refresh
process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information
row hammer
Computer security exploit
CAS latency
time delay between data read command and availability of data in a computer's RAM
flash memory controller
software or hardware component that facilitates data transfer, wear-leveling, error correction, and other important functions between flash memory and the host system
serial presence detect
standardized way to automatically access information about a memory module
Memory map
data structure
Hybrid Memory Cube
variant of computer RAM memory
Dual-ported RAM
Type of random-access memory
Wear leveling
operating principle for certain storage media
memory barrier
synchronization barrier that forces an ordering constraint on memory accesses
transactional memory
concurrency control mechanism, analogous to database transactions for controlling access to shared memory in concurrent computing, that simplifies concurrent programming by allowing a group of load and store instructions to execute in an atomic way
computational RAM
random-access memory with processing elements integrated on the same chip
coalescing
in computer science, the act of merging two adjacent free blocks of memory
Phison
thumb|Phison SSD controller
Phison Electronics Corporation () is a Taiwanese public electronics company that primarily designs, manufactures and sells controllers for NAND flash memory chips. These are integrated into flash-based products such as USB flash drives, memory cards, and solid-state drives (SSDs).
core rope memory
read-only memory in which ferrite cores in a rope act merely as transformers, and whether a word line wire couples or not to the core encodes bits; first used in the 1960s by NASA in Mariner probes and in the Apollo Guidance Computer
Intel 1103
dynamic random-access memory (DRAM) integrated circuit (IC) developed and fabricated by Intel
flat memory model
addressing paradigm modeling memory as one contiguous address space
Interleaved memory
computer memory access architecture
soft error
type of error where a signal or datum is wrong
Recovery Toolbox
software vendor's products family
flash file system
class of file systems designed to run on flash memory
SONOS
SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon",
is a cross sectional structure of MOSFET (metal–oxide–semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays.
Read-write memory
type of computer memory that may be relatively easily written to as well as read from
U61000
thumb|U61000D
Open NAND Flash Interface Working Group
association of electronic companies of NAND flash interface technologies sector

2024–present global memory supply shortage
semiconductor memory supply crisis
in-memory processing
processing data tecnology
base address
memory address serving as a reference point ("base") for other addresses
Memory coherence
RAM consistency methods in multicore computers
Scratchpad memory
high-speed internal memory used for temporary storage
Plated wire memory
variant of core memory
cache on a stick
module containing SRAM used as an L2 cache in mid-1990s computers
cache hierarchy
memory hierarchy concept applied to CPU caches with multiple levels
Universal memory
proposed form of computer storage
programmable metallization cell
new memory technology that uses copper nanowires
PEEK and POKE
low-level commands of the BASIC programming language
Read-modify-write
In computer science, read–modify–write is a class of atomic operations (such as test-and-set, fetch-and-add, and compare-and-swap) that both read a memory location and write a new value into it simultaneously, either with a completely new value or some function of the previous value. These operations prevent race conditions in multi-threaded applications. Typically they are used to implement mutexes or semaphores. These atomic operations are also heavily used in non-blocking synchronization.
Memory ordering
order of accesses to computer memory by a CPU
write-only memory
humorous fictional type of computer memory