Machine code

set of instructions executed directly by a computer's central processing unit (CPU)

In mathematics, an operand is the object of a mathematical operation, i.e., it is the object or quantity that is operated on.

computer code compiled from source code

In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus. In contrast, in CPUs, the opcode is the portion of a machine language instruction that specifies the operation to be performed.

part of the instruction architecture in most processors that determines how machine language instructions find the data they need.

process by which a compiler's code generator converts some intermediate representation of source code into a form that can be readily executed by a machine

instruction in computer program

class of exploits in which a vulnerable computer program misinterprets data as code

machine and assembly-language instruction with no effect

In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification") allowing software to discover details of the processor. It was introduced by Intel in 1993 with the launch of the Pentium and late 486 processors.

several computer machine code instructions that cause a computer's CPU to halt

RDRAND (for "read random") is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy source. It is also known as Intel Secure Key Technology, codenamed Bull Mountain. Intel introduced the feature around 2012, and AMD added support for the instruction in June 2015. RDRAND is available in Ivy Bridge processors and is part of the Intel 64 and IA-32 instruction set architectures.

x86 CPU instruction which pauses execution

type of program control instruction