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Parallel computing

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Slurm
free and open-source job scheduler for Linux and similar computers
Parallel programming model
abstraction of parallel computer architecture, with which it is convenient to express algorithms and their composition in programs
Bit-level parallelism
Parallel Computing Base
OpenACC
OpenACC (for open accelerators) is a programming standard for parallel computing developed by Cray, CAPS, Nvidia and PGI. The standard is designed to simplify parallel programming of heterogeneous CPU/GPU systems.
partitioned global address space
parallel programming model in computer science
MOSIX
MOSIX is a proprietary distributed operating system. Although early versions were based on older UNIX systems, since 1999 it focuses on Linux clusters and grids. In a MOSIX cluster/grid there is no need to modify or to link applications with any library, to copy files or login to remote nodes, or even to assign processes to different nodes – it is all done automatically, like in an SMP.
embarrassingly parallel
problem which is trivially divided into parallelized tasks
Network On Chip
communication subsystem on an integrated circuit
automatic parallelization
Method of improving computer program speed
Template:Flynn's Taxonomy
Wikimedia template
flow-based programming
data-flow programming paradigm
Tesla
GPU microarchitecture designed by NVIDIA
Oracle Grid Engine
batch-queuing system for grid computing
C++ AMP
native programming model that contains elements that span the C++ programming language and its runtime library; provides an easy way to write programs that compile and execute on data-parallel hardware (e.g. GPUs)
POWER10
Power10 is a superscalar, multithreading, multi-core microprocessor family, based on the open source Power ISA, announced in August 2020 and available from September 2021. The processor is designed to have 15 cores available. The main features of Power10 are higher performance per watt and better memory and I/O architectures, with a focus on artificial intelligence (AI) workloads. Each Power10 core has doubled up on most functional units compared to its predecessor POWER9. Power10 is available in a range of IBM models and is supported by operating systems including Linux 5.9 and PowerVM. The b
TeraScale
codename for a family of graphics processing unit microarchitectures
ROCm
ROCm is an Advanced Micro Devices (AMD) software stack for graphics processing unit (GPU) programming. ROCm spans several domains, including general-purpose computing on graphics processing units (GPGPU), high performance computing (HPC), and heterogeneous computing. It offers several programming models: HIP (GPU-kernel-based programming), OpenMP (directive-based programming), and OpenCL.
Distributed memory
multiprocessing memory architecture
Memory-level parallelism
computer architecture feature
Expeed
thumb|right|Expeed logo The Nikon Expeed image/video processors (often styled EXPEED) are media processors for Nikon's digital cameras.
gridMathematica
gridMathematica is a software product sold by Wolfram Research which extends the parallel processing capabilities of its main product Mathematica.
asynchronous array of simple processors
type of computer processor
Memory coherence
RAM consistency methods in multicore computers
Linux-HA
The Linux-HA (High-Availability Linux) project provides a high-availability (clustering) solution for Linux, FreeBSD, OpenBSD, Solaris and Mac OS X which promotes reliability, availability, and serviceability (RAS).
Red Storm
supercomputer architecture designed for the US Department of Energy’s National Nuclear Security Administration Advanced Simulation and Computing Program
Nvidia DGX
deep learning supercomputer system
Apache Samza
open-source distributed stream processing
Uniprocessor system
Computer system with one CPU
JUGENE
right|thumbnail|A schematic overview of a Blue Gene/P supercomputer JUGENE (Jülich Blue Gene) was a supercomputer built by IBM for Forschungszentrum Jülich in Germany. It was based on the Blue Gene/P and succeeded the JUBL based on an earlier design. It was at the introduction the second fastest computer in the world, and the month before its decommissioning in July 2012 it was still at the 25th position in the TOP500 list. The computer was owned by the "Jülich Supercomputing Centre" (JSC) and the Gauss Centre for Supercomputing.
Omni-Path
Omni-Path Architecture (OPA) is a high-performance communication architecture developed by Intel. It aims for low communication latency, low power consumption and a high throughput. It directly competes with InfiniBand. Intel planned to develop technology based on this architecture for exascale computing. The current owner of Omni-Path is Cornelis Networks.
SIMT
execution model used in parallel computing
many-core processor
multi-core processor with a large number of cores
Apache Storm
event processor software
Project Monterey
1990s UNIX coalition
amorphous computing
computational systems
Cellular architecture
type of computer architecture prominent in parallel computing.
IBM Parallel Sysplex
cluster of IBM mainframes
Tilera
Tilera Corporation was a fabless semiconductor company focusing on manycore embedded processor design. The company shipped multiple processors in the TILE64, TILEPro64, and TILE-Gx lines.
FR-V
processor able to process both a very long instruction word (VLIW) and vector processor instructions at the same time
Ganglia
monitoring application
HTCondor
HTCondor is an open-source high-throughput computing software framework for coarse-grained distributed parallelization of computationally intensive tasks.
automatic vectorization
optimization where a computer program is converted from a scalar implementation to a vector implementation
OpenHMPP
OpenHMPP (HMPP for Hybrid Multicore Parallel Programming) - programming standard for heterogeneous computing. Based on a set of compiler directives, standard is a programming model designed to handle hardware accelerators without the complexity associated with GPU programming. This approach based on directives has been implemented because they enable a loose relationship between an application code and the use of a hardware accelerator (HWA).