Joint Test Action Group
Sign in to saveJTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs of and testing printed circuit boards after manufacture.
Article
25 sectionsContents
- History
- Debugging
- Storing firmware
- Boundary scan testing
- Electrical characteristics
- Daisy-chained JTAG (IEEE 1149.1)
- Reduced pin count JTAG (IEEE 1149.7)
- Communications model
- Primitives
- JTAG IEEE Std 1149.1 (boundary scan) instructions
- Boundary scan register
- Example: ARM11 debug TAP
- JTAG facilities
- Halt mode debugging
- Monitor mode debugging
- Common extensions
- Uses
- Client support
- Connectors
- Adapter hardware
- Software development
- {{anchor|Serial_Wire_Debug}} Similar interface standards
- See also
- References
- External links
JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs of and testing printed circuit boards after manufacture.
JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. The interface connects to an on-chip Test Access Port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.