PA-RISC
Sign in to savethumb|Hewlett-Packard|HP PA-RISC 7300LC microprocessor thumb|HP 9000 C110 PA-RISC [[workstation booting Debian GNU/Linux ]]
Key facts
- CPU architecture.image
- PA-RISC logo.svg
- CPU architecture.name
- PA-RISC (HP/PA)
- CPU architecture.designer
- Hewlett-Packard
- CPU architecture.bits
- 64-bit (32→64)
- CPU architecture.introduced
- 1986 (1996 PA-RISC 2.0)
- CPU architecture.version
- 2.0 (1996)
- CPU architecture.design
- RISC
- CPU architecture.encoding
- Fixed
- CPU architecture.branching
- Compare and branch
- CPU architecture.endianness
- Big (PA-RISC 1.0)Big/optional bi (PA-RISC 1.1 and 2.0)
- CPU architecture.extensions
- Multimedia Acceleration eXtensions (MAX), MAX-2
- CPU architecture.open
- No
- CPU architecture.gpr
- 32
- CPU architecture.fpr
- 32 64-bit (16 64-bit in PA-RISC 1.0)
- CPU architecture.successor
- PA-WideWord → Itanium
via Wikipedia infobox
Article
5 sectionsContents
- History
- CPU specifications
- See also
- References
- External links
thumb|Hewlett-Packard|HP PA-RISC 7300LC microprocessor thumb|HP 9000 C110 PA-RISC [[workstation booting Debian GNU/Linux ]]
Precision Architecture RISC (PA-RISC) or Hewlett Packard Precision Architecture (HP/PA or HPPA), is a general purpose computer instruction set architecture (ISA) developed by Hewlett-Packard from the 1980s until the 2000s.