RISC-V
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RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.
Key facts
- CPU architecture.name
- RISC-V
- CPU architecture.image
- RISC-V-logo.svg
- CPU architecture.designer
- University of California, Berkeley
- CPU architecture.bits
- 32, 64, 128
- CPU architecture.design
- RISC
- CPU architecture.type
- Load–store
- CPU architecture.encoding
- Variable
- CPU architecture.branching
- Compare-and-branch
- CPU architecture.endianness
- Little
- CPU architecture.page size
- 4 KiB
- CPU architecture.open
- Yes, royalty free
- CPU architecture.gpr
- 16 or 32 (Includes one always-zero register)
- CPU architecture.fpr
- 32 (Optional; width depends on available extensions)
- CPU architecture.vpr
- 32 (Optional; width depends on hardware)
via Wikipedia infobox
Wikidata facts
- Instance of
- computing platform
- Official name
- RISC-V
- Developer
- University of California, Berkeley
- Official website
- riscv.org/china
- Image
- Yunsup Lee holding RISC V prototype chip.jpg
Show 10 more facts
- copyright license
- BSD licenses
- operating system
- Q7715973
- Commons category
- RISC-V
- email address
- mailto:[email protected]
- web feed URL
- riscv.org/feed
- Stack Exchange tag
- cs.stackexchange.com/tags/risc-v
- inception
- 2010-05-18
- topic's main category
- Category:RISC-V
- source code repository URL
- github.com/riscv
- social media followers
- 22100
via Wikidata · CC0
~79 min read
Encyclopedic overview
36 sectionsContents
- History
- Foundations
- Awards
- Rationale
- ISA base and extensions
- Standard extensions
- Profiles and platforms
- Design
- Register sets
- Memory access
- Immediates
- Subroutine calls, jumps, and branches
- Arithmetic and logic sets
- Atomic memory operations
- Compressed subset
- Embedded subset
- Privileged instruction set
- Bit manipulation
- Packed SIMD
- Vector set
- External debug system
- Implementations
- Strategic background
- Significant for-market developments
- Other developments
- Existing
- In development
- Open source
- End-user hardware
- Software
- Development tools
- See also
- Notes
- References
- Further reading
- External links
RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.
RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025.
Excerpted from Wikipedia’s “RISC-V” article, available under the CC BY-SA 4.0 licence.