Verilog
Sign in to saveAlso known as Verilog HDL, IEEE 1364
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the register-transfer level. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.
Key facts
- Programming language.name
- Verilog
- Programming language.file ext
- .v, .vh
- Programming language.paradigm
- Structured
- Programming language.designer
- Prabhu Goel, Phil Moorby and Chi-Lai Huang
- Programming language.developer
- IEEE
- Programming language.discontinued
- Merged into SystemVerilog
- Programming language.latest release version
- IEEE 1800-2023
- Programming language.typing
- Static, weak
- Programming language.dialects
- Verilog-AMS
- Programming language.influenced by
- Pascal, Ada, C, Fortran
- Programming language.influenced
- SystemVerilog
- Programming language.website
- https://ieeexplore.ieee.org/document/10458102
- Programming language.wikibooks
- Programmable Logic/Verilog
via Wikipedia infobox
Wikidata facts
Show 4 more facts
- file extension
- v
- inception
- 1984-01-01
- Stack Exchange tag
- stackoverflow.com/tags/verilog
- software version identifier
- IEEE 1800-2023
Sources (7)
via Wikidata · CC0
~18 min read
Article
26 sectionsContents
- Overview
- History
- Beginning
- Verilog-95
- Verilog 2001
- Verilog 2005
- SystemVerilog
- Updates since 2009
- Example
- Definition of constants
- Synthesizable constructs
- Initial and always
- Fork/join
- Race conditions
- Operators
- Four-valued logic
- System tasks
- Program Language Interface (PLI)
- Simulation software
- See also
- Additional material
- Similar languages
- References
- External links
- Standards development
- Language extensions
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the register-transfer level. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.
In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.