64-bit microprocessors

Intel processor family

Itanium (; ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for enterprise servers and high-performance computing systems. In the concept phase, engineers said "we could run circles around PowerPC...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting Xeon, and eventually penetrate into t

processor brand by Intel

microprocessor produced by AMD

Opteron is a discontinued x86 server and workstation processor line from AMD, and is the first processor that supports the AMD64 instruction set architecture (known generically as x86-64). It was released on April 22, 2003, with the SledgeHammer core (K8) and was intended to compete in the server and workstation markets, particularly in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture (codenamed Barcelona) were announced on September 10, 2007, featuring a new quad-core configuration. The last released Opteron CPUs are the Piledriver-based Opteron

multi-core microprocessor

series of SoC and SiP processors from Apple

microprocessor

64 bit processor

Epyc (stylized as EPYC) is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.

thumb|right|280px|A MCM containing four POWER5 dies and four 36 MB L3 cache dies. Measuring 3.75in x 3.75in thumb|right|280px|Processor module from an IBM i5 system, containing a POWER5+ DCM thumb|2 way POWER5 CPU, heat-sink removed (damaged CPU die) thumb|IBM POWER5+ 8-way MCM CPUs and cache chips. thumb|IBM POWER5+ 8-way MCM Interface. thumb|IBM POWER5+ 8-way MCM side view. The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The PO

The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect.

The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, enabling RS/6000 and eServer iSeries models of AS/400 computer servers to run on the same processor, as a step toward converging the two lines. The POWER4 was a multicore microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip. The original POWER4 had a c

microprocessor by Sun Microsystems

The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.05. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries). thumb|IBM Power6 CPU base thumb|Power6 ceramic base, heat spreader removed thumb|Power6 ceramic base, top thumb|Power6 ceramic base, contacts ==History== POWER6 was described at the International Solid-State Circuits Confe

Sun Microsystem microprocessor

Intel microprocessor

thumb|right|280px|Dual 375 MHz IBM POWER3-II processors on the CPU module of a RS/6000 44P 270.

POWER7 is a family of superscalar multi-core microprocessors based on the Power ISA 2.06 instruction set architecture released in 2010 that succeeded the POWER6 and POWER6+. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, VT; T. J. Watson Research Center, NY; Bromont, QC and IBM Deutschland Research & Development GmbH, Böblingen, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010. thumb|IBM Power7 4 GHz 8-way CPU and IHS from an IBM 9119 thumb|IBM Power7 4 GHz 8-way CPU IHS top from an IBM 9119 thumb|

RISC microprocessor

right|thumb|180px|NEC VR10000. The R10000, code named T5, is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Pre

POWER9 is a family of superscalar, multithreading, multi-core microprocessors produced by IBM, based on the Power ISA. It was announced in August 2016. The POWER9-based processors are being manufactured using a 14 nm FinFET process, in 12- and 24-core versions, for scale out and scale up applications, and possibly other variations, since the POWER9 architecture is open for licensing and modification by the OpenPOWER Foundation members.

series of Chinese supercomputing processors

family of microprocessors

microprocessor developed by Sun Microsystems

Family of microprocessor cores with ARM microarchitecture

microprocessor developed by Sun Microsystems

microprocessor known by its code name, EV5

thumb|A Toshiba R4000 microprocessor thumb|A Integrated Device Technology|IDT R4000 microprocessor thumb|MIPS R4000 die shot The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industr

thumb|upright=1.6|IBM Power E870 can be configured with up to 80 POWER8 cores and 8 TB of RAM.

family of microprocessor cores with ARM microarchitecture

microprocessor designed by Fujitsu

microprocessor developed by Fujitsu

Power10 is a superscalar, multithreading, multi-core microprocessor family, based on the open source Power ISA, announced in August 2020 and available from September 2021. The processor is designed to have 15 cores available. The main features of Power10 are higher performance per watt and better memory and I/O architectures, with a focus on artificial intelligence (AI) workloads. Each Power10 core has doubled up on most functional units compared to its predecessor POWER9. Power10 is available in a range of IBM models and is supported by operating systems including Linux 5.9 and PowerVM. The b

upright=.8|thumb|An IDT R4600 upright=.8|thumb|IDT R4600 die shot The R4600, code-named "Orion", is a 64-bit microprocessor developed by Quantum Effect Design (QED) that implemented the MIPS III instruction set architecture (ISA). As QED was a design firm that did not fabricate or sell their designs, the R4600 was first licensed to Integrated Device Technology (IDT), and later to Toshiba and then NKK. These companies fabricated the microprocessor and marketed it. The R4600 was designed as a low-end workstation or high-end embedded microprocessor. Users included Silicon Graphics, Inc. (SGI) for

microprocessor also known as "Rainbow Falls"

microprocessor introduced by Oracle Microelectronics in 2011

thumb|NEC VR5000 The R5000 is a 64-bit, bi-endian, superscalar, in-order execution 2-issue design microprocessor that implements the MIPS IV instruction set architecture (ISA) developed by Quantum Effect Design (QED) in 1996. The project was funded by MIPS Technologies, Inc (MTI), also the licensor. MTI then licensed the design to Integrated Device Technology (IDT), NEC, NKK, and Toshiba. The R5000 succeeded the QED R4600 and R4700 as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and Toshiba as the TX50

The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.

microprocessor

thumb|A HP PA-8000 microprocessor The PA-8000 (PCX-U), code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). It was a completely new design with no circuitry derived from previous PA-RISC microprocessors. The PA-8000 was introduced on 2 November 1995 when shipments began to members of the Precision RISC Organization (PRO). It was used exclusively by PRO members and was not sold on the merchant market. All follow-on PA-8x00 processors (PA-8200 to PA-8900, described further below) are based on th

microprocessor developed by Sun Microsystems