Superscalar microprocessors

line of desktop and mobile microprocessors produced by Intel

family of Intel microprocessors

family of Intel microprocessors

method of improving instruction-level parallelism

thumb|Logo used since 2018 for Zen-based Athlon processors thumb|Original AMD Athlon logo

CPU that implements instruction-level parallelism within a single processor

microarchitecture

family of x86 microprocessors introduced in 1999

family of microprocessors introduced in 1998

class of computer architecture in Flynn's taxonomy

Intel processor microarchitecture

RISC-based microprocessor design

microprocessor

integrated part of a processing unit (such as a CPU, or a GPU)

32-bit microprocessor

RISC-based microprocessor design

designation used by Apple Computer and Eyetech to describe a fourth generation of 32-bit PowerPC microprocessors

family of Intel Pentium 1 microprocessors

technique for improving the overall efficiency of superscalar CPUs with hardware multithreading

The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect.

family of third generation 32-bit PowerPC microprocessors

microarchitecture

thumb|right|280px|Dual 375 MHz IBM POWER3-II processors on the CPU module of a RS/6000 44P 270.

RISC microprocessor

right|thumb|180px|NEC VR10000. The R10000, code named T5, is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Pre

The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture (ISA). It was originally known as the RISC System/6000 CPU or, when in an abbreviated form, the RS/6000 CPU, before introduction of successors required the original name to be replaced with one that used the same naming scheme (POWERn) as its successors in order to differentiate it from the newer designs.

The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture. The POWER2 was the successor of the POWER1, debuting in September 1993 within IBM's RS/6000 systems. When introduced, the POWER2 was the fastest microprocessor, surpassing the Alpha 21064. When the Alpha 21064A was introduced in 1993, the POWER2 lost the lead and became second. IBM claimed that the performance for a 62.5 MHz POWER2 was 73.3 SPECint92 and 134.6 SPECfp92.

microprocessor developed by Sun Microsystems

microprocessor known by its code name, EV5

The Rise mP6 was a superpipelined and superscalar microprocessor designed by Rise Technology to compete with the Intel Pentium line.

thumb|A Toshiba R4000 microprocessor thumb|A Integrated Device Technology|IDT R4000 microprocessor thumb|MIPS R4000 die shot The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industr

microprocessor developed by Sun Microsystems

microprocessor developed by Fujitsu

thumb|NEC VR5000 The R5000 is a 64-bit, bi-endian, superscalar, in-order execution 2-issue design microprocessor that implements the MIPS IV instruction set architecture (ISA) developed by Quantum Effect Design (QED) in 1996. The project was funded by MIPS Technologies, Inc (MTI), also the licensor. MTI then licensed the design to Integrated Device Technology (IDT), NEC, NKK, and Toshiba. The R5000 succeeded the QED R4600 and R4700 as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and Toshiba as the TX50

The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.

microprocessor

right|thumb|A PA-7150 microprocessor

processor

microprocessor

thumb|A HP PA-8000 microprocessor The PA-8000 (PCX-U), code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). It was a completely new design with no circuitry derived from previous PA-RISC microprocessors. The PA-8000 was introduced on 2 November 1995 when shipments began to members of the Precision RISC Organization (PRO). It was used exclusively by PRO members and was not sold on the merchant market. All follow-on PA-8x00 processors (PA-8200 to PA-8900, described further below) are based on th

microprocessor developed by Sun Microsystems