AVX-512
Sign in to saveAVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), and then later in a number of AMD and other Intel CPUs (see list below). AVX-512 consists of multiple extensions that may be implemented independently. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations.
~60 min read
Encyclopedic overview
50 sectionsContents
- Instruction set
- Encoding and features
- SIMD modes
- Extended registers
- Opmask registers
- New opmask instructions
- New instructions in AVX-512 foundation
- Blend using mask
- Compare into mask
- Logical set mask
- Compress and expand
- Permute
- Bitwise ternary logic
- Conversions
- Floating-point decomposition
- Floating-point arithmetic
- Broadcast
- Miscellaneous
- New instructions by sets
- Conflict detection
- Exponential and reciprocal
- Prefetch
- 4FMAPS and 4VNNIW
- BW, DQ and VBMI
- Floating-point instructions
- Other instructions
- VBMI2
- VNNI
- IFMA
- VPOPCNTDQ and BITALG
- VP2INTERSECT
- GFNI
- VPCLMULQDQ
- VAES
- BF16
- FP16
- Arithmetic instructions
- Complex arithmetic instructions
- Approximate reciprocal instructions
- Comparison instructions
- Conversion instructions
- Decomposition instructions
- Move instructions
- BMM
- Legacy instructions with EVEX-encoded versions
- CPUs with AVX-512
- Performance
- Reception
- See also
- References
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), and then later in a number of AMD and other Intel CPUs (see list below). AVX-512 consists of multiple extensions that may be implemented independently. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations.
Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions, scatter operations, and permutations. The number of AVX registers is increased from 16 to 32, and eight new "mask registers" are added, which allow for variable selection and blending of the results of instructions. In CPUs with the vector length (VL) extension—included in most AVX-512-capable processors (see )—these instructions may also be used on the 128-bit and 256-bit vector sizes.
Excerpted from Wikipedia’s “AVX-512” article, available under the CC BY-SA 4.0 licence.