SuperH
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
Key facts
- CPU architecture.name
- SuperH (SH)
- CPU architecture.designer
- Hitachi
- CPU architecture.bits
- 32-bit (32 → 64)
- CPU architecture.introduced
- 1992
- CPU architecture.design
- RISC
- CPU architecture.encoding
- SH-2: 16-bit instructionsSH-2A and newer: mixed 16- and 32-bit instructions
- CPU architecture.endianness
- Big
- CPU architecture.open
- Yes, and royalty-free
via Wikipedia infobox
Article
18 sectionsContents
- History
- SH-1 and SH-2
- SH-3
- SH-4
- Licensing
- Continued availability
- J Core
- Models
- SH-2
- SH-2A
- SH-3
- SH-4
- SH-5
- SH-6
- References
- Citations
- Bibliography
- External links
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the register file was smaller and instructions were generally two-operand format. However, for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.