Chisel

The Constructing Hardware in a Scala Embedded Language ( Chisel ) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs . Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control. For more information on the benefits of Chisel see: "What benefits does Chisel offer over classic Hardware Description Languages?" Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework implemented by LLVM CIRCT. Chisel is permissively licensed (Apache 2.0) under the guidance of CHIPS Alliance. What does Chisel code look like? LED blink FIR Filter Getting Started Bootcamp Interactive Tutorial A Textbook on Chisel Build Your Own Chisel Projects Guide For New Contributors Design Verification Documentation Useful Resources Chisel Dev Meeting Data Types Overview Contributor Documentation Useful Resources for Contributors Compiling and Testing Chisel Running Projects Against Local Chisel Chisel Architecture Overview Chisel Sub-Projects Which version should I use? Roadmap The online Chisel Bootcamp is the recommended way to get started with and learn Chisel. No setup is required (it runs in the browser), nor does it assume any prior knowledge of Scala. The classic Chisel tutorial contains small exercises and runs on your computer. Please see the Installation page of the Chisel website for information about how to use Chisel locally. When you're ready to build your own circuits in Chisel, we recommend starting from the Chisel Template repository , which provides a pre-configured project, example design, and testbench. Follow the chisel-template README to get started. If you insist on setting up your own project from scratch, your project needs to depend on both the chisel-plugin (Scalac plugin) and the chisel library. For example, in SBT this could be expressed as: For Chisel prior to v5.0.0, Chisel was published using a different artifact name: svsim is the lightweight testing library for Chisel, included in this repository. chiseltest (Chisel 6.0 and before) is the batteries-included testing and formal verification library for Chisel-based RTL designs and a replacement for the former PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with fork and join with internal and Verilator integration for simulations. Cheat Sheet , a 2-page reference of the base Chisel syntax and libraries ScalaDoc (latest) , a listing, description, and examples of the functionality exposed by Chisel, older versions are also available Gitter , where you can ask questions or discuss anything Chisel Website (source) Scastie (v6.0.0) - cannot generate Verilog (firtool does not work in Scastie) Scastie (v3.6.0) - generates Verilog with legacy Scala FIRRTL Compiler asic-world If you aren't familiar with verilog, this is a good tutorial. This section describes how to get started contributing to Chisel itself, including how to test your version locally against other projects that pull in Chisel using sbt's managed dependencies. You must first install required dependencies to build Chisel locally, please see the installation instructions. In order to run the following unit tests, you will need several tools on your PATH , namely verilator, yosys, espresso, slang, and filecheck. Check that each is installed on your PATH by running which verilator and so on. In order to have you