IA-64
Sign in to saveIA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.
Key facts
- CPU architecture.name
- Intel Itanium architecture
- CPU architecture.designer
- HP and Intel
- CPU architecture.bits
- 64-bit
- CPU architecture.introduced
- 2001
- CPU architecture.design
- EPIC
- CPU architecture.type
- Load–store
- CPU architecture.encoding
- Fixed
- CPU architecture.branching
- Condition register
- CPU architecture.endianness
- Selectable
- CPU architecture.gpr
- 128 (64 bits plus 1 trap bit; 32 are static, 96 use register windows); 64 1-bit predicate registers
- CPU architecture.fpr
- 128
via Wikipedia infobox
Article
12 sectionsContents
- History
- Development
- Production
- Marketing
- End of life
- Architecture
- Instruction execution
- Memory architecture
- Architectural changes
- See also
- References
- External links
IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.
The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per cycle.