クロックゲーティング
Sign in to savetechnique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states)
Wikidata facts
- Instance of
- electronic circuit
- Image
- Gated clk1.png
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- Commons category
- Clock gating
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