technique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states)
Il clock gating è una tecnica di progettazione dei circuiti integrati che permette di ridurre il consumo di potenza dei chip.
Abstract from DBpedia / Wikipedia · CC BY-SA
Discovered by embedding cosine similarity (sentence-transformers MiniLM, 384-dim).