Supplemental Streaming SIMD Extensions 3
Sign in to saveAlso known as SSE3S, SSSE3, SSSE 3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
In the Vinony graph
Vinony's link graph records 165 inbound references to Supplemental Streaming SIMD Extensions 3, and connects out to Intel Core, Advanced Vector Extensions and x86.
Vinony files it under SIMD computing and X86 instructions.
Vinony links it to 14 Wikipedia language editions.
Wikidata facts
- Instance of
- instruction set architecture
- Part of
- Intel 64
Show 2 more facts
- different from
- Streaming SIMD Extensions 3
- start time
- 2006-00-00
Sources (1)
via Wikidata · CC0
~5 min read
Encyclopedic overview
7 sectionsContents
- History
- Functionality
- CPUs with SSSE3
- New instructions
- See also
- References
- External links
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
== History == SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons.
Excerpted from Wikipedia’s “Supplemental Streaming SIMD Extensions 3” article, available under the CC BY-SA 4.0 licence.