MyHDL
Sign in to saveMyHDL is a Python-based hardware description language (HDL).
Source code
MyHDL is a free, open-source package for using Python as a hardware description and verification language. Go to the directory cosimulation/ for your target platform and following the instructions in the README.txt file.
Excerpt from the source-code README · 2,233 chars · not written by Vinony
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Encyclopedic overview
3 sectionsContents
- Conversion examples
- See also
- References
MyHDL is a Python-based hardware description language (HDL).
Features of MyHDL include: The ability to generate VHDL and Verilog code from a MyHDL design. The ability to generate a testbench (Conversion of test benches) with test vectors in VHDL or Verilog, based on complex computations in Python. The ability to convert a list of signals. The ability to convert output verification. The ability to do co-simulation with Verilog. An advanced datatype system, independent of traditional datatypes. MyHDL's translator tool automatically writes conversion functions when the target language requires them.
Excerpted from Wikipedia’s “MyHDL” article, available under the CC BY-SA 4.0 licence.