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wafer-level packaging · Vinony

EntityQ4017648· pop 8· linked from 68 articles

wafer-level packaging

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technology of packaging an integrated circuit while still part of the wafer

Connections

dual in-line package

integrated circuit packaging

International Standard Book Number

integrated circuit

photoelectric effect

printed circuit board

Samsung Galaxy S III

voltage regulator

semiconductor device

semiconductor wafer

surface-mount technology

semiconductor device fabrication

Categories

Chip carriers Electronics manufacturing Semiconductor technology

Sources

wikipedia.externallinksexternallink

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What links here68 pages

three-dimensional integrated circuit

Chip scale package

small-outline integrated circuit

package on a package

integrated circuit packaging

Zig-zag in-line package

Universal Integrated Circuit Card

system in package

surface-mount technology

Thin-Shrink Small Outline Package

through-silicon via

integrated circuit

land grid array

Quad Flat No-leads package

field-programmable gate array

dual in-line package