Verilog-AMS
Sign in to saveVerilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which can be used to solve differential equations in the analog-domain, as well as other problems. Both domains are coupled: analog events can trigger digital actions and vice versa.
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Encyclopedic overview
8 sectionsContents
- Overview
- Code example
- Implementations
- See also
- References
- External links
- General
- Open Source Implementations
Verilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which can be used to solve differential equations in the analog-domain, as well as other problems. Both domains are coupled: analog events can trigger digital actions and vice versa.
== Overview == The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.
Excerpted from Wikipedia’s “Verilog-AMS” article, available under the CC BY-SA 4.0 licence.