File:KL_Sun_UltraSparc.jpg · Wikimedia Commons · See Wikimedia Commons
精简指令集
Sign in to saveAlso known as RISC, reduced instruction set computer
processor executing one instruction in minimal clock cycles
Wikidata facts
- Subclass of
- instruction set architecture
- Image
- KL Sun UltraSparc.jpg
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- opposite of
- complex instruction set computer
- start time
- 1960-01-01
- ACM Classification Code (2012)
- 10010523
- derivative work
- ARM architecture
- topic has template
- Template:RISC-based processor architectures
- different from
- RISC complex
- Commons category
- Reduced Instruction Set Computers
- short name
- RISC
via Wikidata · CC0
Article · 中文
精简指令集计算机（英語：reduced instruction set computer，缩写：RISC）或简译为精简指令集，是计算机中央處理器的一种设计模式。这种设计思路可以想像成是一家模組化的組裝工廠，对指令数目和寻址方式都做了精简，使其实现更容易，指令并行执行程度更好，编译器的效率更高。目前常見的精簡指令集微處理器包括DEC Alpha、、ARM、AVR、MIPS、PA-RISC、Power ISA（包括PowerPC、PowerXCell）、RISC-V和SPARC等。
Abstract from DBpedia / Wikipedia · CC BY-SA